IBM unveils sub-1-nanometer chip design

IBM has unveiled a new semiconductor design it says could push computer chips beyond today’s cutting edge, packing 100 billion transistors onto a silicon chip the size of a fingernail while sharply improving performance and power use.

The Armonk, New York-based company said Thursday that its new “NanoStack” technology is the equivalent of about 0.7 nanometers, potentially making it the first known chip technology below 1 nanometer. IBM said the design is not ready for industrial production, but the company “sees a path to production in as early as the next five years.”

The announcement comes as chipmakers race to increase computing power in smaller devices and as data centers, especially those used for artificial intelligence, face growing pressure over electricity demand. Taiwan’s TSMC, the world’s leading chip manufacturer, has recently begun mass-producing 2-nanometer chips, the current industry benchmark. IBM’s proposed 0.7-nanometer technology would mark a significant step beyond that, though it remains years from mass production.

A nanometer is a billionth of a meter, but in chipmaking the number does not describe the literal size of a chip or its components. It is used to describe how densely transistors, the tiny electronic switches that make up processors, can be packed together. More transistors generally mean faster and more powerful computing, enabling advances in smartphones, laptops, data centers, self-driving cars and artificial intelligence tools.

IBM said tests of its prototype showed “up to 50 percent more performance, or 70 percent greater energy efficiency” than its 2-nanometer node chips. The BBC reported that IBM made similar claims when it introduced its 2-nanometer chip technology in 2021.

The company said the key change is a three-dimensional architecture that stacks transistor layers on top of each other rather than arranging them in a single layer. The approach is part of a broader industry effort to keep increasing transistor density as it becomes harder to extend the decades-long pattern known as Moore’s Law, under which the number of transistors on a chip has roughly doubled every two years.

“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms,” said Jay Gambetta, director of IBM Research. “We’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”

Professor Alan Woodward, a computer scientist at Surrey University, compared the design to “building a big block of flats rather than houses in a city,” the BBC reported. “IBM’s NanoStack is like proposing a 100-story skyscraper,” he said, adding that rivals such as Samsung and Intel are closer to 30- to 50-story buildings with their own 3D chip work. “I think it’s fair to say IBM’s proposals are the most ambitious,” he said.

The 3D approach also brings technical hurdles. Woodward said heat is a challenge because transistors warm as they work, and heat rises. Very thin layers can also prevent transistors from switching off properly, stopping the chip from working.

IBM said the technology also delivers a 40 percent improvement in SRAM memory chips, which act as a processor’s short-term memory and are used in devices including gaming consoles and laptops. Huiming Bu, IBM’s vice president of semiconductors, called that gain “something that we haven’t seen in decades.”

IBM does not manufacture chips itself. CBS News reported that the company licenses its designs to manufacturers such as Japan’s Rapidus, with which it is working to scale 2-nanometer production. Producing chips at this level requires advanced manufacturing equipment, deep technical expertise and billions of dollars in investment. TSMC is also developing 1.4-nanometer technology targeted for mass production around 2028, CBS News reported.